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shadow page tables



 
 
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  #1  
Old October 27th 10, 09:38 PM posted to alt.comp.hardware.amd.x86-64
Prasad
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Posts: 1
Default shadow page tables

Hello All,

I have a question on usage of shadow page tables in virtualized
environment.

AMD processor with virtualization extension support use Address Space
Identifier (ASID) to identify a VM uniquely. The ASID is used to avoid
flushing of TLB entries when host OS switches from one VM to another.

So each TLB entry has two additional tagging information associated
with it ie. ASID and PID of a process.

Tagging the TLB allows a system to support multiple VMs without the
need to flush the TLB when switching
between tasks across VMs.

The Shadow Page Tables translate Guest Physical Memory to the Host
Physical Memory.

I can't understand why can't TLB entries itself translate from Guest
Virtual Memory Address to Host Physical Memory Address.

Why does a TLB translates from Guest Virtual Memory Address to Guest
Physical Memory Address?

Please clarify. Forgive me if I am not supposed to post this question
here.

Thanks and Regards,
Prasad
  #2  
Old October 29th 10, 11:05 AM posted to alt.comp.hardware.amd.x86-64
AGross
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Posts: 18
Default shadow page tables

Uh... http://developer.amd.com/assets/NPT-...1-final-TM.pdf ?

Try amdzone.com forums. There are some hardware engineers there that
can explain this.
 




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